A low noise clock generator for high-resolution time-to-digital convertors
نویسندگان
چکیده
منابع مشابه
A High Resolution First Order Noise-Shaping Vernier Time-to-Digital Converter
Abstract In this paper, we propose a noise reduction method for a Vernier Time-to-Digital Converter (VTDC) using a first-order noise shaping structure and a gated ring oscillator (GRO). An 11bit VTDC with 4 p s effective resolution was designed and developed for a high performance All Digital Frequency Synthesizer (ADFS). The VTDC realized in 180nm CMOS, its power consumption depending on the t...
متن کاملA Low-Power Microcontroller with on-Chip Self-Tuning Digital Clock-Generator for Variable-Load Applications
Clock disabling for power management has been implemented in some microcontrollers, but the wake-up time of Xtal/PLL-based systems is incompatible with fast interrupt response. On the other hand, hardwired on-chip clocking has been used for dedicated circuits. We illustrate the design issues of a general-purpose microcontroller core with a programmable on-chip fullydigital clock generator. The ...
متن کاملDigital Programmable Gaussian Noise Generator
.......................................................................................................................................... 1 Statement of Authorship ................................................................................................................. 3 Acknowledgements ......................................................................................................
متن کاملLow Settling Time All Digital DLL For VHF Application
Settling time is one of the most important parameter in design of DLLs. In this paper we propose a new high speed with low settling time Delay Locked Loop (DLL) in which a digital signal processor (DSP) is used instead of using phase-frequency detector, charge pump and loop filter in conventional DLL. To have better settling time, PRP conjugate gradient algorithm is used to optimize delay of ea...
متن کاملA Superconductive High-Resolution Time-to-Digital Converter
We are developing an ultra-high resolution timeto-digital converter (TDC) based on a novel scheme combining a digital “coarse” TDC and analog “fine” TDC. The coarse TDC is derived from a previously reported RSFQ time digitizer based on binary counters. The fine TDC is based on an analog prescaler. A 31 GHz counter defines the coarse (~32 ps) time resolution, while the prescaler provides a fine ...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: Journal of Instrumentation
سال: 2016
ISSN: 1748-0221
DOI: 10.1088/1748-0221/11/02/c02038